In order to enhance an operating speed of a semiconductor device, generally it is necessary to decrease each capacitance and resistance which each semiconductor element constituting the semiconductor device has while it is in operation, for example, a capacitance of a gate oxide film, a junction capacitance, and a wiring resistance. For scale-down of the semiconductor devices, it is an important problem how a resistance in a source/drain region and a resistance of a gate electrode is decreased, among wiring resistances of the semiconductor element. It is considered that a sheet resistance is preferably made not higher than 10 .OMEGA./.quadrature., if possible.
Conventionally, to make a gate electrode have a lower resistance, the gate electrode is arranged so as to have a two-layer configuration having a refractory metal such as tungsten, or a silicide of such a metal as one layer, and a polysilicon as the other layer. On the other hand, as a method of making the source/drain region have a lower resistance, an impurity implantation dose is increased, or an activation ratio of the impurity is raised by annealing at a higher temperature for activating the impurity.
However, with these above methods, since the impurity is more greatly diffused sideward, characteristics of a semiconductor device such as a transistor remarkably deteriorate due to the short channel effect or the like. To avoid this problem, a method is used whereby the impurity diffused layer, where the source/drain region is to be formed, is made thinner and is made to have a low resistance. Applied to this method is a technology for causing selective reaction between a refractory metal such as Ti and a silicon substrate so as to form silicide, namely, a so-called salicide forming technology. The following description will explain a method for forming an MOS FET (metal-oxide-semiconductor field effect transistor) to which the salicide forming technology is applied, with reference to FIGS. 8(a) through 8(d).
A gate electrode 55 made of polysilicon is formed on a p-type silicon substrate 51 on which an element isolating oxide film 52 is formed, with a gate insulating film 54 provided between the gate electrode 55 and the p-type silicon substrate 51.
Next, using the gate electrode 55 as a mask, an n-type impurity is implanted into the p-type silicon substrate 51 through the gate insulating film 54, so that a low dense impurity diffused layer 56A is formed. Thereafter, only on the side surfaces of the gate electrode 55, silicon oxide films 57 are formed. Furthermore, using the gate electrode 55 and the silicon oxide films 57 as masks, the n-type impurity is implanted into the low dense impurity diffused layer 56A through the gate insulating film 54 so that a high dense impurity diffused layer 56B is formed. As a result, an n-channel MOS transistor having an LDD structure (lightly doped drain structure) is formed, as shown in FIG. 8(a).
In the next stage, exposed parts of the gate insulating film 54 are removed, so as to expose the top surface of the gate electrode 55 and a surface of the high dense impurity diffused layer 56B formed in the p-type silicon substrate 51, as illustrated in FIG. 8(b). Then, Ti is deposited by a sputtering method or the like all over the exposed surface so that a Ti film 58 is formed thereon. Thereafter, an annealing is applied to it in a nitrogen atmosphere at a temperature of 500-700.degree. C. for from 20 seconds to 1 minute, to cause reaction between Ti and silicon, that is, Ti film 58 and the high dense impurity diffused layer 56B. As a result, a TiSi.sub.x film 59 is formed, as shown in FIG. 8(c).
Thereafter, non-reacted Ti is removed, and an annealing at a temperature of 800-850.degree. C. is applied. As a result, an n-channel MOS transistor having a source/drain region 56 with a low resistance and the gate electrode 55 is formed, as illustrated in FIG. 8(d). Finally, an interlayer insulating layer 60 and a metal wire 61 are formed, so that an n-channel MOS transistor as a semiconductor device is completed.
It is known that a refractory metal silicide film such as a TiSi.sub.x film 59 tends to agglomerate thereby having a high resistance, unless it is formed under suitable conditions. Especially, it is known that when an amount of oxygen contained in silicon to be reacted with Ti increases, the Ti silicide film formed by reaction between Ti and silicon tends to agglomerate, thereby having a high resistance. Therefore, in order to form a Ti silicide film having a low resistance, it is necessary that the density of oxygen contained in the silicon is lowered.
Such a phenomenon that the Ti silicide film has a higher resistance with the increase of oxygen in silicon to be reacted with Ti is remarkable especially in a high dense n-type impurity diffused region where As.sup.+ is implanted. The reason seems that when As.sup.+ is implanted, atoms of oxygen contained in the oxide film on the silicon substrate are knocked on by the ion beam and plunge into the inside of the silicon substrate, which is the so-called knock-on phenomenon of oxygen.
On the other hand, in a high dense p-type impurity diffused region, the mass number of the implanted ion can be reduced to about one fifth, by using not BF.sub.2.sup.+ but B.sup.+ as implanted ion. Therefore, in this case, the amount of implanted ion oxygen introduced into the silicon by the knock-on phenomenon drastically decreases.
Therefore, another method whereby the impurity is implanted after the salicide formation process has been also considered. The following description will discuss the method.
First, a gate electrode is formed, then silicon oxide films are formed on side surfaces of the gate electrode, while a top surface of the gate electrode and a surface of an impurity-implanted region are exposed. Thereafter, a Ti film is formed so as to cover the exposed surfaces, and then an annealing at a temperature of from 500 to 700.degree. C. is applied so that a Ti silicide film is formed.
Thereafter, As.sup.+ is implanted through the Ti silicide film, for example, at an implantation dose of 5.times.10.sup.15 ions/cm.sup.2. After a non-reacted part of the Ti film is removed, an annealing for activation, for example, at a temperature of 900.degree. C. for 10 minutes, is applied.
However, for the activation of the implanted ion, an annealing at a temperature of not lower than 850.degree. C. for from 10 to 20 minutes is required, whereas an annealing under such conditions causes agglomeration of the Ti silicide, which increases a wire resistance especially at portions with a narrow wire width.
A method of preventing oxygen from being mixed with the salicide film during the silicide forming reaction is disclosed by the Japanese Publication for Laid-Open Patent Application No. 6-97110/1994 (Tokukaihei 6-97110). According to the method, after depositing Ti on the surface of the silicon substrate, an oxidation-resistant mask is formed thereon, and thereafter the silicide forming reaction is carried out, so that contamination by oxygen is prevented. However, though the method is effectual for preventing the contamination by oxygen during the salicide film forming process, the impurity implantation process for forming a high dense impurity diffused region in the silicon substrate is not described in the foregoing disclosure.